Publications by Jean-Luc Beuchat
International Journals
- Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki.
A Low-Area Unified Hardware Architecture for the AES and the
Cryptographic Hash Function ECHO.
Journal of Cryptographic Engineering, 1(2):101-121, 2011.
- Jean-Luc Beuchat,
Jérémie Detrey,
Nicolas Estibals,
Eiji Okamoto, and
Francisco Rodríguez-Henríquez.
Fast Architectures for the ηT Pairing over
Small-Characteristic Supersingular Elliptic Curves.
In
J. Bruguera, M. Cornea, and D. Das Sarma, editors,
IEEE Transactions on Computers, Special Section on Computer
Arithmetic, 60(2):266-281, 2011.
- Jean-Luc Beuchat,
Hiroshi Doi,
Kaoru Fujita,
Atsuo Inomata,
Piseth Ith,
Akira Kanaoka,
Masayoshi Katouno,
Masahiro Mambo,
Eiji Okamoto,
Takeshi Okamoto,
Takaaki Shiga,
Masaaki Shirase,
Ryuji Soga,
Tsuyoshi Takagi,
Ananda Vithanage, and
Hiroyasu Yamamoto.
FPGA and ASIC Implementations of the ηT
Pairing in Characteristic Three.
Computers and Electrical Engineering, 36(1):73-87, 2010.
- Jean-Luc Beuchat and Jean-Michel Muller.
Automatic Generation of Modular Multipliers for FPGA Applications.
IEEE Transactions on Computers, 57(12):1600-1613, 2008.
- Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey,
Eiji Okamoto, Masaaki Shirase, and Tsuyoshi Takagi.
Algorithms and Arithmetic Operators
for Computing the ηT
Pairing in Characteristic Three.
In W. Geiselmann, Ç.K. Koç, and R. Steinwandt, editors,
IEEE Transactions on Computers,
Special Section on Special-Purpose Hardware for Cryptography and Cryptanalysis,
57(11):1454-1468, 2008.
- Jean-Luc Beuchat, Takanori Miyoshi, Jean-Michel Muller, and Eiji Okamoto.
Horner's Rule-Based Multiplication over GF(p) and GF(pn): A Survey.
International Journal of Electronics, 95(7):669-684, 2008.
- Jean-Luc Beuchat and Jean-Michel Muller.
Modulo M Multiplication-Addition: Algorithms and
FPGA Implementation. Electronics Letters, 40(11):654-655, 2004.
- Jean-Luc Beuchat and Jacques-Olivier Haenni.
Von Neumann's 29-state Cellular Automaton: A Hardware
Implementation. IEEE Transactions on Education,
43(3):300-308, 2000.
- Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni,
Jean-Luc Beuchat, André Stauffer, and Andrés Perez-Uribe.
Static and Dynamic Configurable Systems.
IEEE Transactions on Computers, 48(6):556-564, 1999.
International Conferences
- Jean-Luc Beuchat.
Hardware Architectures for the Cryptographic Tate Pairing. In Pairing-Based Cryptography - Pairing 2012.
- Nuray At, Jean-Luc Beuchat, and Ismail San.
Compact Implementation of Threefish and Skein on FPGA. In
Proceedings of the 5th IFIP International Conference on New
Technologies, Mobility and Security. IEEE Press, 2012.
- Diego F. Aranha,
Jean-Luc Beuchat,
Jérémie Detrey, and
Nicolas Estibals.
Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves.
In O. Dunkelman, editor, Topics in Cryptology - CT-RSA 2012, number 7178 in
Lecture Notes in Computer Science, pages 98-115. Springer, 2012.
- Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki.
Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA. In
J. Bian, Q. Zhou, and K. Zhao, editors,
Proceedings of the 2010 International Conference on Field-Programmable
Technology - FPT 2010,
pages 170-177. IEEE Press, 2010.
- Jean-Luc Beuchat,
Jorge Enrique González Díaz,
Shigeo Mitsunari,
Eiji Okamoto,
Francisco Rodríguez-Henríquez, and
Tadanori Teruya.
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves.
In M. Joye, A. Miyaji, and A. Otsuka, editors, Pairing-Based Cryptography - Pairing 2010,
number 6487 in Lecture Notes in Computer Science, pages 21-39.
Springer, 2010. © Springer-Verlag.
- Jean-Luc Beuchat,
Emmanuel López-Trejo,
Luis Martínez-Ramos,
Shigeo Mitsunari, and
Francisco Rodríguez-Henríquez.
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves.
In J.A. Garay, A. Miyaji, and A. Otsuka, editors, Cryptology and Network Security - CANS 2009,
number 5888 in Lecture Notes in Computer Science, pages 413-432.
Springer, 2009. © Springer-Verlag.
- Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals,
Eiji Okamoto, and Francisco Rodríguez-Henríquez.
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.
In C. Clavier and K. Gaj, editors,
Cryptographic Hardware and Embedded Systems - CHES 2009,
number 5747 in Lecture Notes in Computer Science, pages 225-239.
Springer, 2009. © Springer-Verlag. Best paper award.
- Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey,
Eiji Okamoto, and Francisco Rodríguez-Henríquez.
A Comparison Between Hardware Accelerators for the Modified Tate Pairing
over F2m and F3m.
In S.D. Galbraith and K.G. Paterson, editors, Pairing 2008,
number 5209 in Lecture Notes in Computer Science, pages 297-315.
Springer, 2008. © Springer-Verlag.
- Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, and Eiji Okamoto.
Arithmetic Operators for Pairing-Based Cryptography. In
P. Paillier and I. Verbauwhede, editors,
Cryptographic Hardware and Embedded Systems - CHES 2007,
number 4727 in Lecture Notes in Computer Science, pages 239-255. Springer, 2007.
© Springer-Verlag. Best paper award.
- Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase,
Tsuyoshi Takagi, and Eiji Okamoto.
A Coprocessor for the Final Exponentiation of the ηT Pairing
in Characteristic Three. In
C. Carlet and B. Sunar, editors,
Proceedings of WAIFI 2007, number
4547 in Lecture Notes in Computer Science, pages 25-39. Springer, 2007.
© Springer-Verlag.
- Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, and Eiji Okamoto.
An Algorithm for the ηT Pairing Calculation in
Characteristic Three and its Hardware Implementation. In
P. Kornerup and J.-M. Muller, editors,
Proceedings of the 18th IEEE Symposium on Computer Arithmetic,
pages 97-104, IEEE Computer Society, 2007.
- Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, and Eiji Okamoto.
Multiplication over Fpm on FPGA: A Survey. In
P.C. Diniz, E. Marques, K. Bertels, M.M. Fernandes, and J.M.P. Cardoso, editors,
Reconfigurable Computing: Architectures, Tools and Applications - Proceedings of ARC 2007,
number 4419 of Lecture Notes in Computer Science, pages 214-225. Springer, 2007.
© Springer-Verlag.
- Rachid Beguenane, Jean-Luc Beuchat, Jean-Michel Muller, and Stéphane Simard.
Modular Multiplication of Large Integers on FPGA.
In Proceedings of the 39th Asilomar Conference on Signals, Systems & Computers,
pages 1361-1365. IEEE Signal Processing Society, 2005.
- Jean-Luc Beuchat and Jean-Michel Muller.
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Numbers.
In S. Vassiliadis, N. Dimopoulos, and S. Rajopadhye, editors,
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors,
pages 303-308. IEEE Computer Society, 2005.
- Jean-Luc Beuchat.
FPGA Implementations of the RC6 Block Cipher.
In P.Y.K. Cheung, G.A. Constantinides, and J.T. de Sousa, editors,
Field-Programmable Logic and Applications,
number 2778 of Lecture Notes in Computer Science,
pages 101-110. Springer, 2003.
© Springer-Verlag.
- Jean-Luc Beuchat, Laurent Imbert, and Arnaud Tisserand.
Comparison of Modular Multipliers on FPGAs.
In F.T. Luk, editor,
Advanced Signal Processing Algorithms, Architectures and Implementations XIII,
volume 5205, pages 490-498. The International Society for Optical Engineering (SPIE), 2003.
- Jean-Luc Beuchat.
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.
In E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, and L. Thiele, editors,
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors,
pages 412-422. IEEE Computer Society, 2003.
- Jean-Luc Beuchat.
Some Modular Adders and Multipliers for
Field Programmable Gate Arrays. In Proceedings of the 17th
International Parallel & Distributed Processing
Symposium. IEEE Computer Society, 2003.
- Jean-Luc Beuchat and Arnaud Tisserand.
Small Multiplier-based Multiplication and Division Operators for Virtex-II Devices.
In M. Glesner, P. Zipf, and M. Renovell editors,
Field-Programmable Logic and Applications - Reconfigurable
Computing Is Going Mainstream, number 2438 in Lecture Notes in Computer Science, pages 513-522. Springer,
2002. © Springer-Verlag.
- Jean-Luc Beuchat and Eduardo Sanchez. An On-Line
Arithmetic-Based Reconfigurable Neuroprocessor. In J. Rolim,
editor, Parallel and Distributed Processing, number 1586
in Lecture Notes in Computer Science, pages 700-702. Springer, 1999. © Springer-Verlag.
- Jean-Luc Beuchat and Eduardo Sanchez. Using On-Line
Arithmetic and Reconfiguration for Neuroprocessor
Implementation. In J. Mira and J.V. Sánchez-Andrés,
editors, Engineering Applications of Bio-Inspired
Artificial Neural Networks, number 1607 in Lecture Notes in
Computer Science, pages 129-138. Springer, 1999. © Springer-Verlag.
- Jean-Luc Beuchat, Jacques-Olivier Haenni, and Eduardo Sanchez.
Hardware Reconfigurable Neural Networks. In J. Rolim,
editor, Parallel and Distributed Processing, number 1388
in Lecture Notes in Computer Science, pages 91-98. Springer, 1998. © Springer-Verlag.
- Jean-Luc Beuchat and Eduardo Sanchez. A Reconfigurable
Neuroprocessor with On-chip Pruning. In L. Niklasson,
M. Bodén, and T. Ziemke, editors, Perspectives
in Neural Computing - ICANNN 1998, pages 1159-1164. Springer, 1998.
Book Chapters
- Jean-Luc Beuchat and Arnaud Tisserand.
Opérateurs arithmétiques sur circuits FPGA.
In J.-C. Bajard and J.-M. Muller, editors, Calcul et
arithmétique des ordinateurs, Traité IC2, pages 109-152.
Lavoisier, 2004.
- Moshe Sipper, Eduardo Sanchez, Jacques-Olivier Haenni, Jean-Luc
Beuchat, André Stauffer, and Andrés Perez-Uribe.
From configurable circuits to bio-inspired systems. In
H.-N. Teodorescu, D. Mlynek, A. Kandel, and H.-J. Zimmermann,
editors, Intelligent Systems and Interfaces, vol. 15 of
Intelligent Technologies Series. Kluwer Academic Publishers,
Boston, 2000.
National Journals
- 山崎 哲平, Jean-Luc Beuchat, and 岡本 栄司. BLAKE-256，BLAKE-512のコンパクトな統合実装.
In IEICE 暗号と情報セキュリティ実装技術小特集号, J95-A(5):416-424, 2012.
- Jean-Luc Beuchat. Being a foreign researcher in Japan. Bulletin of Department of Risk Engineering, 7:14-16, 2011.
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- Jean-Luc Beuchat and Arnaud Tisserand. Évaluation
polynomiale en-ligne de fonctions élémentaires sur FPGA.
Technique et Science Informatiques, 23(10):1247-1267, 2004.
- Jean-Luc Beuchat, Jacques-Olivier Haenni,
Hector Fabio Restrepo, Christof Teuscher,
Francisco J. Gómez, and
Eduardo Sanchez. Approches matérielles et logicielles de
l'algorithme de chiffrement IDEA. Technique et Science Informatiques,
21(2):203-224, 2002.
- Jean-Luc Beuchat, Jacques-Olivier Haenni, Erik Bruchez, and
Eduardo Sanchez. Une plate-forme pour le développement
et le prototypage de systèmes reconfigurables.
Informatik/Informatique, (1):21-24, 1998.
National Conferences
- Vithanage Ananda, 猪俣 敦夫, 岡本 栄司, 岡本 健, 金岡 晃, 上遠野 昌良, 志賀 隆明,
白勢 政明, 曽我 竜司, 高木 剛, 土井 洋, 藤田 香, Jean-Luc Beuchat, 満保 雅浩, and
山本 博康. ペアリング演算ASICの開発.
In Proceedings of CSEC 2008, pages 31-35. 2008.
- Jean-Luc Beuchat and Jean-Michel Muller. RN-codes :
algorithmes d'addition, de multiplication et d'élévation au carré.
In SympA'2005 : 10ème édition du SYMPosium
en Architectures nouvelles de machines, pages 73-84, 2005.
- Jean-Luc Beuchat and Jean-Michel Muller.
Multiplication-addition modulaire : algorithmes itératifs et
implantations sur FPGA. In M. Auguin, F. Baude, D. Lavenier, and
M. Riveill, editors, Actes de RenPar'15, CFSE'3 et SympAAA'2003,
pages 235-242, 2003.
- Jean-Luc Beuchat and Arnaud Tisserand.
Opérateur en-ligne sur FPGA pour l'implantation de quelques fonctions
élémentaires. In
Actes de la conférence Sympa'8 - Symposium en
Architectures Nouvelles de Machines, pages 267-274, 2002.
- Jean-Luc Beuchat, Jacques-Olivier Haenni, Christof Teuscher,
Francisco J. Gómez, Hector Fabio Restrepo, and
Eduardo Sanchez. Une comparaison entre quelques implantations
logicielles et matérielles de l'algorithme de chiffrement
IDEA. In Actes de la conférence Sympa'6 - Symposium en
Architectures Nouvelles de Machines, pages 25-34, 2000.
- Jean-Luc Beuchat. Conception d'un neuroprocesseur
reconfigurable proposant des algorithmes d'apprentissage et
d'élagage : une première étude.
In F. Alexandre and Jean-Daniel Kant, editors,
Actes des journées NSI'98, 1998.
Ph.D. and Master's Theses
- Jean-Luc Beuchat.
Étude et conception d'opérateurs arithmétiques optimisés pour circuits programmables.
Ph.D. thesis, École Polytechnique Fédérale de Lausanne, 2001.
- Jean-Luc Beuchat.
Reconnaissance de caractères manuscrits à l'aide de réseaux neuromimétiques.
Master's thesis,
École Polytechnique Fédérale de Lausanne and IDIAP, 1997.
Unpublished Work
- Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, and Teppei Yamazaki.
A Low-Area Unified Hardware Architecture for the AES and the
Cryptographic Hash Function Grøstl.
Cryptology ePrint Archive, Report 2012/535, 2012.
- Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki.
A Compact FPGA Implementation of the SHA-3 Candidate ECHO.
Cryptology ePrint Archive, Report 2010/364, 2010.
- Nidia Cortez-Duarte, Francisco Rodríguez-Henríquez, Jean-Luc Beuchat, and Eiji Okamoto.
A Pipelined Karatsuba-Ofman Multiplier over GF(397)
Amenable for Pairing Computation.
Cryptology ePrint Archive, Report 2008/127, 2008.
- Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, and Eiji Okamoto.
A Refined Algorithm for the ηT Pairing Calculation in Characteristic Three.
Cryptology ePrint Archive, Report 2007/311, 2007.
- Jean-Luc Beuchat.
Further Comments on Residue-to-Binary Converters Based on New Chinese Remainder Theorems.
ArXiv:0707.3732v2.
- Jean-Luc Beuchat.
A Family of Modulo (2n+1) Multipliers.
LIP Research Report 2004-39. 2004. (Also available
as Inria Research Report 5316, 2004.)
- Jean-Luc Beuchat, Nicolas Sendrier, Arnaud Tisserand, and Gilles Villard.
FPGA Implementation of a Recently Published Signature Scheme.
LIP Research Report 2004-14, 2004.
- Jean-Luc Beuchat.
More on Modulo 2n-1 Addition.
LIP Research Report 2003-14, 2003.
- Jean-Luc Beuchat, Christof Teuscher, Francisco J. Gómez, and
Hector Fabio Restrepo.
Un premier prototype de coprocesseur cryptographique.
Rapport technique de projet CTI, École Polytechnique Fédérale de Lausanne, 2000.
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© 2004-2012 Jean-Luc Beuchat, All Rights Reserved.
Last modified: Fri Oct 5 14:36:32 JST 2012