Jean-Luc Beuchat

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• Vitæ
• Photography
• Research
• Teaching Material
• Events
• Contact

Who am I?

I am an associate professor in the Graduate School of Systems and Information Engineering at the University of Tsukuba, Japan.

My research focuses on the hardware implementation of arithmetic circuits for cryptographic applications.

My curriculum vitæ is available in pdf.

Photography

• My picture gallery

Research

• Complete list of publications
• Co-author index
• Selected publications:
  • Jean-Luc Beuchat. Hardware Architectures for the Cryptographic Tate Pairing. In Pairing-Based Cryptography - Pairing 2012.

    Slides:

    [ pdf ]

  • Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, and Nicolas Estibals. Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves. In O. Dunkelman, editor, Topics in Cryptology - CT-RSA 2012, number 7178 in Lecture Notes in Computer Science, pages 98-115. Springer, 2012.

    DOI:	[ 10.1007/978-3-642-27954-6_7 ]
    Article:	[ pdf ][ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

  • Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki. A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO. Journal of Cryptographic Engineering, 1(2):101-121, 2011.

    DOI:	[ 10.1007/s13389-011-0009-8 ]
    Article:	[ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

    Open-source VHDL code:

    [ gzipped tar file ]

  • Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, and Francisco Rodríguez-Henríquez. Fast Architectures for the η_T Pairing over Small-Characteristic Supersingular Elliptic Curves. In J. Bruguera, M. Cornea, and D. Das Sarma, editors, IEEE Transactions on Computers, Special Section on Computer Arithmetic, 60(2):266-281, 2011.

    DOI:	[ 10.1109/TC.2010.163 ]
    Article:	[ pdf ][ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

  • Jean-Luc Beuchat, Jorge Enrique González Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, and Tadanori Teruya. High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. In M. Joye, A. Miyaji, and A. Otsuka, editors, Pairing-Based Cryptography - Pairing 2010, number 6487 in Lecture Notes in Computer Science, pages 21-39. Springer, 2010. © Springer-Verlag.

    DOI:	[ 10.1007/978-3-642-17455-1_2 ]
    Article:	[ pdf ][ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

  • Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, and Tsuyoshi Takagi. Algorithms and Arithmetic Operators for Computing the η_T Pairing in Characteristic Three. In W. Geiselmann, Ç.K. Koç, and R. Steinwandt, editors, IEEE Transactions on Computers, Special Section on Special-Purpose Hardware for Cryptography and Cryptanalysis, 57(11):1454-1468, 2008.

    DOI:	[ 10.1109/TC.2008.103 ]
    Article:	[ pdf ][ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

  • Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, and Francisco Rodríguez-Henríquez. A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F_2^m and F_3^m. In S.D. Galbraith and K.G. Paterson, editors, Pairing-Based Cryptography - Pairing 2008, number 5209 in Lecture Notes in Computer Science, pages 297-315. Springer, 2008. © Springer-Verlag.

    DOI:	[ 10.1007/978-3-540-85538-5_20 ]
    Article:	[ pdf ][ bib ]

    Pre-print version:

    [ www ][ pdf ][ bib ]

Teaching Material

• Jean-Luc Beuchat. An Introduction to Pairing-Based Cryptography. Computer Science Department, Centro de Investigación y de Estudios Avanzados del IPN, Mexico City, Mexico. July 2008. [ Slides ]
• Jean-Luc Beuchat. Algorithms and Number Systems for Digital Arithmetic. Laboratory of Cryptography and Information Security, University of Tsukuba, Tsukuba, Japan. April 2006. [ Slides ]
• Jean-Luc Beuchat. Une introduction à l'arithmétique des ordinateurs. Département des sciences appliquées, Université du Québec à Chicoutimi, Chicoutimi, Canada. 2004.
  1. Quelques systèmes de numération. [ Slides ]
  2. Une famille d'algorithmes de multiplication modulaire. [ Slides ]
  3. Arithmétique modulo (2ⁿ+1) - Implantation sur FPGA et application à l'algorithme de cryptage IDEA. [ Slides ]
  4. Conception de processeurs spécifiques pour des applications cryptographiques. [ Slides ]
• Jean-Luc Beuchat. Quelques additionneurs et multiplieurs modulaires sur FPGA. École Normale Supérieure de Lyon, Lyon, France. 2004. [ Slides ]
• Jean-Luc Beuchat and Jacques-Olivier Haenni. Automate cellulaire autoréplicateur de von Neumann. Logic Systems Laboratory, Swiss Federal Institute of Technology at Lausanne. March 2001. [ pdf ][ Slides ]
• Jean-Luc Beuchat. Systèmes neuromimétiques à apprentissage supervisé. Logic Systems Laboratory, Swiss Federal Institute of Technology at Lausanne. April 1999. [ pdf ]

Forthcoming Events

• Pairing 2012, Cologne, Germany, May 16-18, 2012
• WAIFI 2012, Bochum, Germany, July 16-19, 2012
• Crypto 2012, Santa Barbara, USA, August 19-23, 2012
• CHES 2012, Leuven, Belgium, September 9-12, 2012
• Arith 21, Austin, Texas, April 7-10, 2013

Contact